The present invention relates to a non-volatile semiconductor memory device having two storages, each comprised of a charge storage film comprised of a plurality of stacked dielectric films, at the two ends of a channel formation region and capable of independently storing two bits of information in the storages and a method of producing the same.
Known in the art are so-called xe2x80x9cMONOSxe2x80x9d (metal oxide nitride oxide semiconductor) type and other non-volatile semiconductor memory devices having charge storage films comprised of a stacked plurality of dielectric films and storing information by controlling amounts of charges stored in charge traps in the charge storage films.
Recently, technology taking note of the fact that it is possible to inject a charge into part of a region of distribution of dispersed charge traps by the conventional CHE (channel hot electron) injection method and independently write binary information at a source side and a drain side of a charge storage film so as to enable independent storage of two bits of information in one memory cell has been reported.
For example, in xe2x80x9c2000 Symposium on VLSI Technology, pp. 122-123xe2x80x9d, charge storage films are separately provided on the source side and the drain side, control electrodes are provided on the charge storage films, and word gate electrodes are provided at a center portion of a channel between the control electrodes in a state with a single-layer dielectric film not having a charge holding ability interposed. The word gate electrodes are connected to a word line, while the control electrodes are laid in a direction orthogonal to the word line and are controlled separately from the word gate electrodes. Therefore, the controllability of a position of charge injection and the charge injection efficiency can be improved and, as a result, a high speed write operation is attained.
The memory cells, which are called xe2x80x9ctwin MONOS cellsxe2x80x9d, have word gate electrodes repeated at a certain interval in the row direction, and have sidewall type conductive layers on wall surfaces on the two sides of the same in the row direction. ONO (oxide-nitride-oxide) films, namely, charge storage films having a charge holding ability, are provided directly under the sidewall type conductive layers. As opposed to this, single layers of dielectric films are formed directly under the word gate electrodes, thus these parts do not have any charge holding ability.
The sidewall type conductive layers and the word gate electrodes are used as masks for introducing N-type impurities to substrate locations exposed between adjacent sidewall type conductive layers to form N+-type impurity regions serving as sources or drains.
The above paper did not disclose a specific production method, but a twin MONOS cell has the following problems in production and structure.
In twin MONOS cells, the word gate electrodes are formed, then sidewall type conductive layers are formed at their sides. Thus, a step of connecting the word gate electrodes to the word line is necessary.
Further, the word gate electrodes in twin MONOS cells first need to be patterned to parallel line shapes long in the column direction. At this time, normally, the word gate electrode material is deposited, then patterns of a resist are formed on it and the word gate electrode material is processed by an etching method having strong anisotropy, for example, by RIE (reactive ion etching), using the resist as a mask. The resist patterns normally are tapered forward in sectional shapes at their side surfaces, and the resist recesses somewhat at the time of etching, so the sides of the word gate electrodes after the processing also are tapered forward. Further, even when a resist is not used and a material which does not recess at the time of etching is used, forward tapering is liable to arise to a certain extent at the side surfaces of the word gate electrodes after the processing due to the effect of sidewall deposits at the time of etching.
The word gate electrodes for example need to be simultaneously processed when patterning the word lines to isolate them for cells. However, at this time, since the control gates are already formed at the sidewalls of the word gate electrodes in a state having insulation films interposed, the word gate electrodes have to be selectively etched and removed while digging holes having trapezoidal sectional shapes. Accordingly, at the time of this etching, the bottom sides of the side surfaces of the reverse tapered control electrodes are difficult to etch and conductive residue easily is produced in these portions along the control electrodes. If conductive residue is produced, short-circuit occur between the word lines.
Further, the sidewall type conductive layers are formed in ring shapes circling the periphery of the line shaped conductive layers for forming the word gate electrodes. If the sidewall type conductive layers are used for the control electrodes as they are, a control electrode on the source side and a control electrode on the drain side would become electrically short-circuited. Therefore, to supply different voltages to the control electrode on the source side and the control electrode on the drain side, the two control electrodes have to be isolated. This isolation cannot be performed all together in another step, for example, at the time of processing the word lines, so for example a step of forming an etching mask opened only at the two end portions of the line shaped conductive layers for forming the word gate electrodes, removing an insulation film covering the sidewall type conductive layers through the openings, and cutting the conductive layers by etching becomes necessary.
Furthermore, in a twin MONOS cell, since ONO films are formed directly under the sidewall type conductive layers, the ONO films contacting the channel formation region extend long in the column direction along the sidewall type conductive layers. During operation, data is written by injecting charges to a region of an ONO film crossing with a channel (hereinafter referred to as a storage), while data is erased by draining the stored charge to the substrate side or by injecting a reverse conductivity type charge. When repeating this rewrite operation, a charge is liable to accumulate continuously in an adjacent region of the storage. Further, a leak path to the outside of the channel is liable to be formed by the charge. When erasing data by draining the stored charges, which are electrons, from the entire surface of the channel, since the adjacent region is also under control of a control electrode in the same way as the storage and electrons accumulated at the adjacent region are also drained at the same time, this does not become much of a problem. However, particularly when injecting a charge having a reverse polarity to a storage for erasing stored charge, if a charge having a polarity of a direction turning on the channel, for example, an electron hole in the case of an N-type channel, is accumulated in an adjacent region of the storage, a leak path will be easily formed. The resultant decline of the leak characteristic-therefore becomes a problem.
A first object of the present invention is to eliminate the need for a step of connecting word gate electrodes and a word line by structurally enabling formation of the word gate electrodes and word line (second control electrode) as an integral member.
A second object of the present invention is to prevent production of conductive residue which would cause short-circuit between word lines and to structurally eliminate the need for a step of cutting apart two control electrodes in a single cell.
A third object of the present invention is to prevent an unnecessary charge from accumulating in an adjacent region of a storage in a direction along a control electrode or between storages and to achieve a structure where no leakage current occurs.
To attain the above first and second objects, a non-volatile semiconductor memory device according to a first aspect of the present invention comprises a memory cell, the memory cell comprising a channel formation region comprised of a semiconductor, charge storage films each comprised of a stacked plurality of dielectric films and having a charge holding ability, two storages comprised of regions of the charge storage films overlapping two ends of the channel formation region, a single-layer dielectric film contacting the channel formation region between the storages, two first control electrodes formed one each of the storages so that main regions on mutually facing surfaces become forward tapered, and a second control electrode buried in a space between the two first control electrodes in a state insulated from the first control electrodes and contacting the single-layer dielectric film.
The memory cell further comprises two impurity regions comprised of a semiconductor of a reverse conductivity type from the above channel formation region and mutually separated across the channel formation region and two auxiliary layers formed on the two impurity regions close to each surface of the first control electrodes facing the outside of the memory cell.
The auxiliary layers are comprised of conductive layers close to outside surfaces of the first control electrodes in a state with dielectric films interposed or layers of polycrystalline silicon or amorphous silicon doped with an impurity of the same conductivity type as the impurity regions. Alternatively, the auxiliary-layers are comprised of dielectric layers close to the outside surfaces of the first control electrodes.
In a configuration arranging a plurality of memory cells in a matrix, two first control electrodes straddling from the two sides in the width direction an auxiliary layer shared by two memory cells adjacent in the row direction may be made sidewall shapes or may be made shapes connected above the auxiliary layer. First control electrodes of the latter shape are comprised of conductive layers covering the two sides and upper surface of the auxiliary layer and have a lower interconnection resistance comparing with that in the sidewall shapes.
To achieve the third object, a non-volatile semiconductor memory device according to a second aspect of the present invention comprises a plurality of memory cells, each of the memory cells comprising a channel formation region comprised of a first conductivity type semiconductor, first and second impurity regions comprised of a second conductivity type semiconductor and separated from each other straddling the channel formation region, control electrodes arranged long in a direction orthogonal to a direction of separation of the first and second impurity regions and shared by a plurality of memory cells, and charge storage films each comprised of a plurality of dielectric films formed at layers directly below the control electrodes and storing information in portions overlapping the channel formation region. The memory device wherein memory cells adjacent in the direction orthogonal to the direction of separation of the first and second impurity regions being electrically isolated by dielectric isolation layers; and pairs of the first impurity regions and pairs of second impurity regions of the adjacent memory cells isolated by the dielectric isolation layer being connected respectively by conductive layers.
To achieve the first and second objects, a method of producing a non-volatile semiconductor memory device according to a third aspect of the present invention comprises a method of producing a non-volatile semiconductor memory device comprising a channel formation region comprised of a first conductivity type semiconductor, two impurity regions separated from each other straddling the channel formation region and comprised of a second conductivity type semiconductor, two first control electrodes formed on two ends of the channel formation region close to the two impurity regions in a state with charge storage films, each comprised of a plurality of dielectric films, interposed, and a second control electrode facing the channel formation region between the first control electrodes in a state with a single-layer dielectric film interposed and arranged long in the direction of separation of the impurity regions, including the steps of forming auxiliary layers in line shapes long in a direction orthogonal to a direction of separation of the impurity regions on the impurity regions or semiconductor regions where the impurity regions are to be formed; forming the charge storage film on surfaces of the auxiliary layers and a surface of the channel formation region; forming the first control electrodes along the auxiliary layers in a state with the charge storage film interposed; removing part of the charge storage film by etching using the first control electrodes as a mask; forming a single-layer dielectric film on a surface of the channel formation region exposed by the removal of the charge storage film and surfaces of the first control electrodes; and forming the second control electrodes on the single-layer dielectric film and the auxiliary layers.
To achieve the third object, the method of producing a non-volatile semiconductor memory device according to the third aspect of the present invention further includes the steps of forming dielectric isolation layers in parallel line shapes long in one direction in a conductor of a first conductivity type and forming auxiliary layers comprised of polycrystalline silicon or amorphous silicon doped with a second conductivity type impurity in parallel line shapes long in a direction orthogonal to the dielectric isolation layers and forming the impurity regions of the second conductivity type at semiconductor locations overlapping regions of arrangement of the auxiliary layers between the dielectric isolation layers.
According to the non-volatile semiconductor memory device according to the first aspect and the method of producing a non-volatile semiconductor memory device according to the third aspect of the present invention, since the main regions on facing surfaces of two first control electrodes comprising one memory cell become forward tapered, residue of a conductive substance which induces short-circuit between second control electrodes when processing the second control electrodes is not generated. Further, formation of word lines is completed just by processing the second control electrodes.
According to the non-volatile semiconductor memory device according to the second aspect of the present invention, the regions of the charge storage films adjacent to the portions of the charge storage films forming storages at the two sides in the longitudinal direction of the first control electrodes ride up over the dielectric isolation layers between the channel formation regions. By just making the thickness of the dielectric isolation layers for example about several tens of nm, even when charges are stored in the adjacent regions, the effect of the charges to the semiconductor directly under the dielectric isolation layers becomes extremely weak comparing with that in conventional cases.